The forming of grooves in semiconductor surfaces is well known and has many established uses, one of which is for dielectric isolation. These grooves can be formed by channel etching or anisotropic etching as is well known in the art.
Usually in the prior art, the grooves are refilled by various layers of oxides, nitrides, polycrystalline material. Thereafter, the wafers are subjected to mechanical polishing to smooth out the surfaces and provide a planar surface into which active devices are formed. One of the problems in this process is the establishment of a planar surface at the point within the wafer that is desired. Techniques have been provided whereby carbide layers or nitride layers are formed at the various points within the wafer at which the polishing stops. The nitride or carbide layer is harder than the surrounding material and, the polishing becomes noticeably more difficult when such layer is exposed and the polishing therefore stops when the harder layer is exposed.
Such polishing back techniques have been the only techniques available for re-establishing the planarity of the wafer once the refill steps have been formed. However, these polishing techniques introduce additional problems. For example, the nitride and carbide layers are more difficult to form than an oxide layer. The oxide layer is formed by the oxidation of the semiconductor wafer itself or through chemical vapor deposition techniques which are more particularly known. The polishing back step is a very difficult procedure when the polishing must be accurate to within plus or minus a few microns.